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Ordering Information
Part Number
Logic
Input
Threshold
Package
Packing
Method
Quantity
per Reel
FAN3213TMX
FAN3214TMX
Dual Inverting Channels
Dual Non-Inverting Channels
FAN3213TMX_F085 (1)
Dual Inverting Channels
TTL
SOIC-8
Tape & Reel
2,500
FAN3214TMX_F085 (1)
Dual Non-Inverting Channels
Note:
1. Qualified to AEC-Q100
Package Outlines
Figure 2. SOIC-8 (Top View)
Thermal Characteristics (2)
Package
8-Pin Small Outline Integrated Circuit (SOIC)
Θ JL (3)
38
Θ JT (4)
29
Θ JA(5)
87
Ψ JB (6)
41
Ψ JT (7)
2.3
Unit
°C/W
Notes:
2. Estimates derived from thermal simulation; actual values depend on the application.
3. Theta_JL ( Θ JL ): Thermal resistance between the semiconductor junction and the bottom surface of all the leads
(including any thermal pad) that are typically soldered to a PCB.
4. Theta_JT ( Θ JT ): Thermal resistance between the semiconductor junction and the top surface of the package,
assuming it is held at a uniform temperature by a top-side heatsink.
5. Theta_JA ( Θ JA ): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking,
and airflow. The value given is for natural convection with no heatsink, using a 2S2P board, as specified in
JEDEC standards JESD51-2, JESD51-5, and JESD51-7, as appropriate.
6. Psi_JB ( Ψ JB ): Thermal characterization parameter providing correlation between semiconductor junction
temperature and an application circuit board reference point for the thermal environment defined in Note 5. For
the SOIC-8 package, the board reference is defined as the PCB copper adjacent to pin 6.
7. Psi_JT ( Ψ JT ): Thermal characterization parameter providing correlation between the semiconductor junction
temperature and the center of the top of the package for the thermal environment defined in Note 5.
? 2008 Fairchild Semiconductor Corporation
FAN3213 / FAN3214 ? Rev. 1.0.5
2
www.fairchildsemi.com
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